As an aside, pipelining of loops and functions is possible via simple pragmas in HLS. What does work, is implementing the module with input values to the recursive function as follows: "module fact1 ( input wire clk_i, input wire reset_i, output wire [ 7 : 0 ] fact0_o, output wire [ 7 : 0 ] fact1_o); For example, assign, case, while, wire, reg, and, or, nand, and module. They should not be used as identifiers. Verilog keywords also include compiler directives, and system tasks and functions. Gate Level Modelling. Verilog has built-in primitives like logic gates, transmission gates and switches. May 02, 2017 · Verilog rule of thmb 2: drive a Verilog wire with assign statement or port output, and drive a Verilog reg from an always block. If you want to drive a physical connection with combinatorial logic inside an [email protected](*) block, then you have to declare the physical connection as Verilog reg . REG * We write a value to a variable and that value is stored until next assignment…This is referred to as procedural assignment. The last assignment determines the current value of the variable.